#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#define MAX 100
#define INF 99999
int graph[MAX][MAX];
int numIntersections = 0;
void initGraph(int n)
{
numIntersections = n;
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++) graph[i][j] = (i == j) ? 0 : INF;
}void addRoad(int src, int dest, int weight)
{
graph[src][dest] = weight; graph[dest][src] = weight;
}void dijkstra(int start)
{
int dist[MAX],
visited[MAX],
parent[MAX];
for (int i = 0; i < numIntersections; i++)
{
dist[i] = INF;
visited[i] = 0;
parent[i] = -1;
}
dist[start] = 0;
for (int count = 0; count < numIntersections - 1; count++)
{
int min = INF, u;
for (int v = 0; v < numIntersections; v++)
{
if (!visited[v] && dist[v] <= min)
{
min = dist[v];
u = v;
}
}
visited[u] = 1;
for (int v = 0; v < numIntersections; v++)
{
if (!visited[v] && graph[u][v] && graph[u][v] != INF && dist[u] + graph[u][v] < dist[v]) { dist[v] = dist[u] + graph[u][v]; parent[v] = u; } } } printf("Shortest distances from intersection %d:\n", start);
for (int i = 0; i < numIntersections; i++)
{
printf("To %d: %d\n", i, dist[i]); }
}
void showNeighbors(int node)
{
printf("Intersections directly connected to %d:\n", node);
for (int i = 0; i < numIntersections; i++)
{
if (graph[node][i] != 0 && graph[node][i] != INF)
printf(" -> %d (distance: %d)\n", i, graph[node][i]);
}
}
int main()
{
int n, roads, src, dest, weight, start; printf("Enter number of intersections: ");
scanf("%d", &n);
initGraph(n);
printf("Enter number of roads: "); scanf("%d", &roads);
printf("Enter each road (format: src dest weight):\n");
for (int i = 0; i < roads; i++)
{
scanf("%d %d %d", &src, &dest, &weight); addRoad(src, dest, weight);
}
printf("Enter start intersection for shortest path: ");
scanf("%d", &start);
dijkstra(start);
printf("Enter intersection to view neighbors: ");
scanf("%d", &src); showNeighbors(src);
return 0;
}// Gate primitives: OR, NAND, NOR, XOR
module gates(
input wire a,
input wire b,
output wire or_out,
output wire nand_out,
output wire nor_out,
output wire xor_out
);
assign or_out = a | b;
assign nand_out = ~(a & b);
assign nor_out = ~(a | b);
assign xor_out = a ^ b;
endmodule
// Half Adder
module half_adder(
input wire a,
input wire b,
output wire sum,
output wire carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
// Full Adder
module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
// 4-bit Carry Lookahead Adder
module cla_4bit(
input wire [3:0] a,
input wire [3:0] b,
input wire cin,
output wire [3:0] sum,
output wire cout,
output wire pg,
output wire gg
);
wire [3:0] p, g, c;
assign p = a ^ b;
assign g = a & b;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & c[0]);
assign c[3] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & c[0]);
assign cout = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & c[0]);
assign sum = p ^ c;
assign pg = &p;
assign gg = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]);
endmodule
// 3-to-8 Decoder
module decoder_3to8(
input wire [2:0] in,
output reg [7:0] out
);
always @(*) begin
out = 8’b0;
out[in] = 1’b1;
end
endmodule
// 8-to-3 Encoder (binary output)
module encoder_8to3(
input wire [7:0] in,
output reg [2:0] out
);
integer i;
always @(*) begin
out = 3’b000;
for (i = 0; i < 8; i = i+1)
if (in[i]) out = i[2:0];
end
endmodule
// Gray to Binary (4-bit)
module gray_to_binary_4bit(
input wire [3:0] gray,
output wire [3:0] binary
);
assign binary[3] = gray[3];
assign binary[2] = gray[3] ^ gray[2];
assign binary[1] = binary[2] ^ gray[1];
assign binary[0] = binary[1] ^ gray[0];
endmodule
// Binary to Gray (4-bit)
module binary_to_gray_4bit(
input wire [3:0] binary,
output wire [3:0] gray
);
assign gray[3] = binary[3];
assign gray[2] = binary[3] ^ binary[2];
assign gray[1] = binary[2] ^ binary[1];
assign gray[0] = binary[1] ^ binary[0];
endmodule
// 2-bit Comparator: greater-than, less-than, equal
module comparator_2bit(
input wire [1:0] a,
input wire [1:0] b,
output wire agt,
output wire alt,
output wire ae
);
assign agt = (a > b);
assign alt = (a < b);
assign ae = (a == b);
endmodule
// —————- Group 2: Multiplexers, Flip‑Flops, Counters —————-
// 2-to-1 Multiplexer
module mux_2to1(
input wire a,
input wire b,
input wire sel,
output wire y
);
assign y = sel ? b : a;
endmodule
// 4-to-1 Multiplexer using case
module mux_4to1(
input wire [1:0] sel,
input wire [3:0] in,
output reg y
);
always @(*) begin
case (sel)
2’d0: y = in[0];
2’d1: y = in[1];
2’d2: y = in[2];
2’d3: y = in[3];
default: y = 1’b0;
endcase
end
endmodule
// D Flip‑Flop with synchronous reset
module d_ff(
input wire d,
input wire clk,
input wire rst_n,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 1’b0;
else
q <= d;
end
endmodule
// JK Flip‑Flop
module jk_ff(
input wire j,
input wire k,
input wire clk,
input wire rst_n,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 1’b0;
else begin
case ({j,k})
2’b00: q <= q;
2’b01: q <= 1’b0;
2’b10: q <= 1’b1;
2’b11: q <= ~q;
endcase
end
end
endmodule
// T Flip‑Flop
module t_ff(
input wire t,
input wire clk,
input wire rst_n,
output reg q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 1’b0;
else if (t)
q <= ~q;
end
endmodule
// 3-bit Up-Counter
module up_counter_3bit(
input wire clk,
input wire rst_n,
output reg [2:0] count
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
count <= 3’b000;
else
count <= count + 1;
end
endmodule
// 4-bit Up/Down Counter
module up_down_counter(
input wire clk,
input wire rst_n,
input wire updown, // 1 = up, 0 = down
output reg [3:0] count
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
count <= 4’b0000;
else if (updown)
count <= count + 1;
else
count <= count – 1;
end
endmodule
// Ring Counter (4-bit)
module ring_counter_4bit(
input wire clk,
input wire rst_n,
output reg [3:0] q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 4’b0001;
else
q <= {q[2:0], q[3]};
end
endmodule
// Johnson Counter (4-bit)
module johnson_counter_4bit(
input wire clk,
input wire rst_n,
output reg [3:0] q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 4’b0000;
else
q <= {~q[0], q[3:1]};
end
endmodule
// —————- Group 3: Sequential Algorithms —————-
// 8-bit Booth Multiplier
module booth_multiplier_8bit(
input signed [7:0] x,
input signed [7:0] y,
output signed [15:0] product
);
reg signed [17:0] A;
reg signed [8:0] Q;
reg Q_1;
integer i;
always @(*) begin
A = 0;
Q = y;
Q_1 = 0;
for (i = 0; i < 8; i = i+1) begin case ({Q[0], Q_1}) 2’b01: A = A + x; 2’b10: A = A – x; endcase // arithmetic right shift A,Q,Q_1 {A, Q, Q_1} = {A[17], A, Q} >>> 1;
end
end
assign product = {A[8:1], Q};
endmodule
// Factorial using for-loop (combinational up to 8!)
module factorial(
input wire [3:0] n,
output reg [31:0] fact
);
integer i;
always @(*) begin
fact = 1;
for (i = 1; i <= n; i = i+1)
fact = fact * i;
end
endmodule
// Simple SRAM Model (16×8)
module sram_16x8(
input cs, we,
input [3:0] addr,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] mem [0:15];
always @(*) begin
if (cs) begin
if (we)
mem[addr] = din;
else
dout = mem[addr];
end else
dout = 8’bZ;
end
endmodule
// File I/O Testbench Stub: writes values 0-15 to fileifdef SIM module file_io_tb; integer fid; integer i; initial begin fid = $fopen("output.txt","w"); for (i = 0; i < 16; i = i+1) $fwrite(fid, "%0d -> %b\n", i, i); $fclose(fid); $finish; end endmodule endif
// —————- Group 4: FSMs and Peripherals —————-
// Mealy FSM: 0101 Detector
module mealy_0101(
input wire din,
input wire clk,
input wire rst_n,
output reg y
);
reg [1:0] state, next_state;
localparam S0=2’d0, S1=2’d1, S2=2’d2, S3=2’d3;
// next-state and output logic
always @(*) begin
next_state = S0;
y = 1'b0;
case (state)
S0: begin
if (!din) next_state = S1;
else next_state = S0;
end
S1: begin
if (din) next_state = S2;
else next_state = S1;
end
S2: begin
if (!din) next_state = S3;
else next_state = S0;
end
S3: begin
if (din) begin
next_state = S2;
y = 1'b1;
end else next_state = S1;
end
endcase
end
// state register
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= S0;
else
state <= next_state;
endendmodule
// Moore FSM: 0101 Detector
module moore_0101(
input wire din,
input wire clk,
input wire rst_n,
output reg y
);
reg [2:0] state, next_state;
localparam S0=3’d0, S1=3’d1, S2=3’d2, S3=3’d3, S4=3’d4;
// next-state logic
always @(*) begin
next_state = S0;
case (state)
S0: next_state = din ? S0 : S1;
S1: next_state = din ? S2 : S1;
S2: next_state = din ? S0 : S3;
S3: next_state = din ? S4 : S1;
S4: next_state = din ? S0 : S1;
endcase
end
// output logic
always @(*) begin
y = (state == S4);
end
// state register
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= S0;
else
state <= next_state;
endendmodule
// 7-Segment Display Driver (common cathode)
module seven_seg_driver(
input wire [3:0] digit,
output reg [6:0] seg // segments a–g
);
always @(*) begin
case (digit)
4’h0: seg = 7’b1000000;
4’h1: seg = 7’b1111001;
4’h2: seg = 7’b0100100;
4’h3: seg = 7’b0110000;
4’h4: seg = 7’b0011001;
4’h5: seg = 7’b0010010;
4’h6: seg = 7’b0000010;
4’h7: seg = 7’b1111000;
4’h8: seg = 7’b0000000;
4’h9: seg = 7’b0010000;
default: seg = 7’b1111111; // blank
endcase
end
endmodule
// Matrix Keypad Scanner (4×4)
module keypad_scanner(
input wire clk,
input wire rst_n,
input wire [3:0] row,
output reg [3:0] col,
output reg [3:0] keycode
);
reg [1:0] scan_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
scan_state <= 0;
else
scan_state <= scan_state + 1;
end
always @(*) begin
col = 4'b1111;
case (scan_state)
2'd0: col = 4'b1110;
2'd1: col = 4'b1101;
2'd2: col = 4'b1011;
2'd3: col = 4'b0111;
endcase
end
always @(*) begin
keycode = 4'hF;
casex ({col, row})
8'b1110_1110: keycode = 4'h1;
8'b1110_1101: keycode = 4'h2;
/* ... full mapping here ... */
default: keycode = 4'hF;
endcase
endendmodule
// Stepper Motor Driver (Wave Drive)
module stepper_wave(
input wire clk,
input wire rst_n,
output reg [3:0] coil
);
reg [1:0] step;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
step <= 0;
else
step <= step + 1;
end
always @(*) begin
case (step)
2’d0: coil = 4’b0001;
2’d1: coil = 4’b0010;
2’d2: coil = 4’b0100;
2’d3: coil = 4’b1000;
default: coil = 4’b0000;
endcase
end
endmodule
// LCD Controller Stub: 16×2 Character Display (HD44780)
module lcd_controller(
input wire clk,
input wire rst_n,
output reg rs,
output reg rw,
output reg en,
output reg [7:0] data
);
// Initialization and write state machine would go here
// This is a stub for structural integration
endmodule
// —————- Group 5: Interfacing Programs —————-
// Up-Down Counter on LEDs (counts 0–15 up or down based on select)
module updown_counter_led(
input wire select, // 1 = up, 0 = down
input wire clk,
input wire rst_n,
output reg [3:0] q
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 4’b0000;
else if (select)
q <= q + 1;
else
q <= q – 1;
end
endmodule
// Seven-Segment Display Driver with External Digit Input
module seven_seg_driver(
input wire [3:0] digit,
output reg [6:0] seg // segments a–g
);
always @(*) begin
case (digit)
4’h0: seg = 7’b1000000;
4’h1: seg = 7’b1111001;
4’h2: seg = 7’b0100100;
4’h3: seg = 7’b0110000;
4’h4: seg = 7’b0011001;
4’h5: seg = 7’b0010010;
4’h6: seg = 7’b0000010;
4’h7: seg = 7’b1111000;
4’h8: seg = 7’b0000000;
4’h9: seg = 7’b0010000;
default: seg = 7’b1111111;
endcase
end
endmodule
// Matrix Keypad Interface: Scans and outputs ASCII code
module keypad_interface(
input wire clk,
input wire rst_n,
input wire [3:0] row,
output reg [3:0] col,
output reg [7:0] ascii
);
reg [1:0] scan_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
scan_state <= 0;
else
scan_state <= scan_state + 1;
end
always @(*) begin
col = 4'b1111;
case (scan_state)
2'd0: col = 4'b1110;
2'd1: col = 4'b1101;
2'd2: col = 4'b1011;
2'd3: col = 4'b0111;
endcase
end
always @(*) begin
case ({col, row})
8'b1110_1110: ascii = 8'h31; // '1'
8'b1110_1101: ascii = 8'h32; // '2'
8'b1110_1011: ascii = 8'h33; // '3'
8'b1110_0111: ascii = 8'h41; // 'A'
8'b1101_1110: ascii = 8'h34; // '4'
8'b1101_1101: ascii = 8'h35; // '5'
8'b1101_1011: ascii = 8'h36; // '6'
8'b1101_0111: ascii = 8'h42; // 'B'
8'b1011_1110: ascii = 8'h37; // '7'
8'b1011_1101: ascii = 8'h38; // '8'
8'b1011_1011: ascii = 8'h39; // '9'
8'b1011_0111: ascii = 8'h43; // 'C'
8'b0111_1110: ascii = 8'h2A; // '*'
8'b0111_1101: ascii = 8'h30; // '0'
8'b0111_1011: ascii = 8'h23; // '#'
8'b0111_0111: ascii = 8'h44; // 'D'
default: ascii = 8'h00;
endcase
endendmodule
// Stepper Motor Full-Step Driver
module stepper_full(
input wire clk,
input wire rst_n,
output reg [3:0] coil
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= 0;
else
state <= state + 1;
end
always @(*) begin
case (state)
2’d0: coil = 4’b1100;
2’d1: coil = 4’b0110;
2’d2: coil = 4’b0011;
2’d3: coil = 4’b1001;
default: coil = 4’b0000;
endcase
end
endmodule
// 16×2 LCD Character Interface (stub)
module lcd_interface(
input wire clk,
input wire rst_n,
output reg rs,
output reg rw,
output reg en,
output reg [7:0] data
);
// Example initialization sequence for ‘HELLO’
// This is a behavioral stub; actual timing and states omitted
endmodule
// End of Group 5